Electronic systems disposed in a high force environment

ABSTRACT

A high acceleration object includes an electronic system which is operable at accelerations in excess of 20,000 g. Connections between integrated circuit chips and other portions of the electronic system are provided by metallization patterns disposed on polymer dielectric layers which are self-supporting across gaps between components. A high density interconnect structure is disposed within the cavity of a hermetically sealed package.

This application is a continuation of application Ser. No. 07/586,330,filed Sep. 18, 1990, abandoned, which is a continuation of applicationSer. No. 07/374,890, filed Jul. 3, 1989, now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of electronic systems, andmore particularly, to high acceleration objects containing electronicsystems.

BACKGROUND INFORMATION

Modern electronic systems normally include integrated circuits.Integrated circuits themselves are substantially unaffected by highaccelerations such as 20,000 g to 100,000 g or higher, where "g" is theacceleration due to gravity, since they are monolithic, relativelysmall, low mass structures. Consequently, such integrated circuitsthemselves are suitable for use in high acceleration objects such asrockets, systems which are launched as projectiles and so forth.Integrated circuits are normally connected into a larger electronicsystem by packaging them in packages which help to protect theintegrated circuit and facilitate connecting them into the largerelectronic system. Normally, the integrated circuit is connected topackage conductors by wire bonds and after mounting of the integratedcircuit, the package is hermetically sealed by a metallic lid whichspans the cavity in which the integrated circuit and its wire bonds aredisposed.

Unfortunately, when such packages are exposed to accelerations on theorder of 20,000 g or more, the wire bonds collapse against theintegrated circuit and the package (the lid is also deformed inward intocontact with the wire bonds and/or contact pads) creating short circuitsand breaking some of the wires. Both of these effects disable theintegrated circuit and the electronic system in which it is connected.Consequently, for use in high acceleration environments, an electronicsystem must be free of wire bonds which can be damaged by that highacceleration.

There is a need in high acceleration objects for electronic systemswhich can withstand high accelerations, both while they are not inoperation and while they are in active operation.

OBJECTS OF THE INVENTION

Accordingly, a primary object of the present invention is to provide ahigh acceleration object with an electronic system which can survive thehigh accelerations the object is intended to undergo.

Another object is to provide an electronic system which is fabricated atall levels in a manner to withstand high accelerations.

Still another object of the invention is to provide a high accelerationobject with an electronic system which is free of wire bonds.

SUMMARY OF THE INVENTION

The above and other objects which will become apparent from thespecification as a whole, including the drawings, are accomplished inaccordance with one embodiment of the present invention byinterconnecting integrated circuits in a high acceleration object with ahigh density interconnect system in which a dielectric layer is disposedover the integrated circuits and any gaps between them and supportsconductors which interconnect the integrated circuits of the system in amanner which is immune to acceleration induced damage for accelerationsin the range from 20,000 g to 100,000 g and higher.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter which is regarded as the invention is particularlypointed out and distinctly claimed in the concluding portion of thespecification. The invention, however, both as to organization andmethod of practice, together with further objects and advantagesthereof, may best be understood by reference to the followingdescription taken in connection with the accompanying drawings in which:

FIG. 1 is a perspective cross-section view of a portion of a prior artelectronic system disposed in a mobile object;

FIG. 2 illustrates the prior art system of FIG. 1 after exposure to highacceleration or shock in the upward direction;

FIG. 3 is a perspective, cross-section partially cut away view of a highacceleration object including an electronic system in accordance withthe present invention;

FIG. 4 is a cross-section view of the FIG. 3 structure during highacceleration;

FIGS. 5-7 illustrate steps in the process of fabricating the structureof FIG. 4; and

FIG. 8 is a plan view of a modified embodiment of the FIG. 4 structure.

DETAILED DESCRIPTION

In FIG. 1, an object 8, including an electronic system 10, comprises astructural portion 20 of the object, an integrated circuit 30 and apackage 40 in which the integrated circuit is packaged. The integratedcircuit 30 has a plurality of contact pads 32 disposed on an uppersurface thereof and a back metallization 34 disposed on a back or lowersurface thereof. This integrated circuit is mounted in a package 40 by asolder or adhesive layer 38. The package 40 includes a shoulder orplateau 42 on which are disposed conductive runs or lands 44 to whichthe contact pads 32 of the integrated circuit are connected by wirebonds 50. The package 40 is a typical prior art package designed for usewith wire bonds to connect the integrated circuit to the packageconductors. Typically, the recess 45 in which the chip 30 is disposed is400 mils (10.2 mm) square and the chip is 350×370 mils (8.9×9.4 mm).Thus, where the chip 30 is centered in the recess 45, a gap of between15 and 25 mils (0.38-0.63 mm) exists between the edge of the chip 30 andthe shoulder 42 of the package. This gap is easily bridged by the wirebonds 50.

It will be understood that the manner in which the package contact lands44 extend to the outside of the package and the type of lead provided onthe outside of the package varies in accordance with the type ofpackage. As is well known in the integrated circuit art, the term "wirebonds" is a term of art referring to fine wires which have one endsolderless bonded to a contact pad of one portion of an electronicstructure and the other end solderless bonded to a contact pad ofanother portion of the structure. "Wire bonds" are sometime referred toas "nail head bonds" because of an enlargement of the wire at the endthereof at which the first bond of a wire bond is formed or wedge bondsin which the wire is crushed in spots to form the solderless bond."Solderless bonded" means without solder and usually involvesthermocompression bonding or ultrasonic bonding. The wire bond wires 50for low power integrated circuits are typically 1 mil (25 microns) indiameter and 0.3-0.4 inch (0.76-1.27 cm) long. These are delicate wireswhich are adequate for use in normal fixed or low acceleration objects.However, when subjected to shock or high accelerations, the wire bondwires 50 are easily bent or deflected.

Object 8 is illustrated in FIG. 2 following exposure to a highacceleration (greater than about 30,000 g) in the positive Z-directionin FIG. 2. As can be seen, all of the wire bond wires 50 within thepackage 40 have been bent down in the negative Z-direction in a mannerwhich creates short circuits and breaks some of the wires 50 as at 54where they extend across the gap 43 between the integrated circuit 30and the package shoulder 42. Even in an absence of the gap 43, shortcircuits would result from the collapse of the wire bond wires. Further,the package lid 49 has been stretched and deformed downward in thefigure in a manner in which it contacts and shorts contact pads 32 ofthe integrated circuit and the bond wires 50. These broken wires andshort circuits disable the electronic system 10 or parts of it.

A high acceleration in the XY plane bends the bond wires substantiallyinto the XY plane and causes failures due to bond wire breakage, bondwires contacting contact pads from which they should be isolated, and soforth. Similarly, a high acceleration in the negative Z directionstretches the bond wires upward breaking or dislodging some of them. Thelid also bows outward. Thus, failure modes are present in wire bondsystems in response to high acceleration in any direction, although theacceleration at which failures first occur may vary with the orientationof the package relative to the direction of acceleration. For thesereasons, wire bonding is not an acceptable connection technique forelectronic systems for use in high acceleration environments.

In FIG. 3, a high acceleration object in accordance with the presentinvention including electronic circuitry 110 therein is shown generallyat 108. In FIG. 3, reference numerals in the one hundreds are utilized.Those reference numerals ending in the same two digits as referencenumerals in FIGS. 1 and 2 identify corresponding structures and may notbe discussed at this point. For the function or purpose of thosestructures not discussed at this point, the reader is referred to theearlier discussion of the similar structures in FIGS. 1 and 2. Thepackage 140 is like the package 40, however, the method and structurewhich is used to connect the integrated circuit contact pads 132 to thepackage contact lands 144 is vastly different. A high densityinterconnect system such as that disclosed in U.S. Pat. No. 4,783,695,entitled "Multichip Integrated Circuit Packaging Configuration andMethod" issued in the name of C. W. Eichelberger et al. is used toconnect the chip contact pads 132 to the package lands 144. A method offorming that structure is disclosed in copending application Ser. No.240,367, filed Aug. 30, 1988, as a continuation of application Ser. No.912,458 filed Sep. 26, 1986, and entitled "Method and Apparatus forPackaging Integrated Circuit Chips Employing a Polymer Film OverlayLayer". Both of these documents are incorporated herein by reference.

In FIG. 3, a polymer dielectric layer 164 is disposed over theintegrated circuit chip 130 and over the shoulder 142 of the package140. This dielectric layer bridges or spans the gap 143 between theintegrated circuit and the shoulder 142 of the package. The dielectriclayer covers the contact pads 132 on the integrated circuit and at leastthe portion of the contact lands 144 nearest the integrated circuit. Avia hole 166 is provided in the dielectric layer 164 at each locationwhere it is desired to have one of the conductors 168 which are disposedon the upper surface of the dielectric layer 164 make electrical contactto an underlying chip contact pad 132 or package contact land 144. InFIG. 3, only a single dielectric layer 164 and a single layer ofconductors 168 is illustrated for clarity in the drawing. Wherenecessary, or desirable, additional dielectric layers may be disposedover the layer 164 and additional conductor layers may be disposed overthose dielectric layers. Connections are made between subsequentconductor layers and the layer 168 through via holes in the overlyingdielectric layer. A block 170 of solid dielectric material is disposedbetween the lid 149 and the high density interconnect system disposed onintegrated circuit 130.

The dielectric layer 164 bridges the gap 143 between the edge of thesemiconductor chip 130 and the package shoulder 142 and supports theconductor 168 over this gap. Typically, the dielectric layer 164 is aKAPTON® polyimide film which is available from DuPont de Nemours Companyand is preferably 1-2 mils (25-50 microns) thick. The conductors 168 arepreferably copper films 0.1-0.5 mils (2-10 microns) thick (ideally about5 microns thick) with an adhesion promotion layer such as titanium ortungsten adjacent the dielectric film 164. Such a conductor 1 mil (25microns) wide and 25 mils (635 microns) long has a mass of only about0.73×10⁻⁶ grams. As such, the force on such a conductor undergoing100,000 g acceleration is only about 6.4 pounds per square inch (psi).That force is sufficient to deflect the dielectric film 164 andconductor 168 in the general manner illustrated in FIG. 4 in thevicinity of the gap 143. This deflection is within the elastic toleranceof both the dielectric film 164 and the ductile copper conductor 168 (ofabout 30%). Consequently, the integrated circuit 130 and its connectionto the package contact lands 144 are not adversely affected by 100,000 gaccelerations. Unfortunately, the same cannot be said for the packagelid 149, which in the prior art, typically has an unsupported span of 1to 2 inches (25-50 mm), which for a steel package lid 10-20 mils thickresults in a force in excess of 640 psi on the center of the lid at100,000 g acceleration. Consequently, in the absence of dielectric block170, the lid would deform in the same manner as illustrated in FIG. 2.That deformation of the lid could result in short circuits between thelid and the conductors within the package in the absence of thedielectric block 170. To prevent this adverse effect, the soliddielectric block, layer or pad 170 disposed within the package betweenthe chip and the lid should have sufficient strength to support (atleast partially) the lid under high acceleration and to thereby ensurethat even in the deformed state of the lid, the integrated circuit andthe conductors thereon are electrically insulated from the lid. Thedielectric block 170 should have a sufficient stiffness (durometerreading) to survive the acceleration and continue to hold the lid out ofcontact with the chip 130 and the wiring thereover. Since the connectionstructure is itself crush resistant, this ensures survival and continuedoperation of the electronic system 110 of which the integrated circuit130 forms a part.

A silicone rubber pad may be used as the solid dielectric buffer betweenthe integrated circuit chip and the inside of the package lid provided abuffer polyimide layer is disposed between that silicone rubber pad andany exposed polyimide films of the packaging structure in order toisolate the package polyimide films from the silicone rubber pad. Thesilicone rubber pad helps to support the package lid 149 and ensuresthat even if the lid is severely deformed by acceleration, that lid doesnot come into contact with the conductors of the high densityinterconnect structure. This ensures, that even in a deformed state, thelid will not render the electronic system inoperative.

The accelerations which the resulting object and its electronics canwithstand can be maximized by tailoring the recess 145 to match theactual chip size, thereby minimizing the gap between the chip and thepackage shoulder or by filling the gap 145 with a dielectric materialsuch as the ULTEM polyetherimide material discussed hereinafter as anadhesive for the KAPTON polyimide film. Either of these techniquesreduces both the unsupported span across which the dielectric layer 164extends and the mass of the dielectric layer and the conductorsextending across this gap.

It will be noted that in the FIG. 3 and 4 structure, the dielectriclayer 164 is recessed within the package below the sealing ring 148 ofthe package. The height of the sidewall portion 146 of the package inprior art packages, is typically 50-80 mils (1.25-2 mm) and isdetermined by the expected height to which the wire bond wires 50 ofFIG. 1 extend above the shoulder 42 of that prior art package. Thisheight or depth is substantially larger than is required with the highdensity interconnect system since the high density interconnect systemprovides a substantially planar connection structure. The method offabricating the interconnect structure in the package 140 will now bediscussed in connection with FIGS. 5-7.

As illustrated and described in U.S. Pat. No. 4,783,695 and patentapplication Ser. No. 240,367, now U.S. Pat. No. 4,933,042 referred toabove, a high density interconnect structure is preferably formed on aflat substrate containing recesses for the integrated circuit chipswhose depth is selected to dispose the upper surface of the integratedcircuits in substantially the same plane as the upper surface of thesubstrate on which conductors are disposed. This facilitates thelamination of the first dielectric layer across the integrated circuitchips and the substrate. The substrate is preferably a ceramic such asalumina (Al₂ O₃).

The polyimide film 164 cannot be applied in the small cavity of thispackage using the specific techniques illustrated and described in theU.S. patent application Ser. No. 240,367 referred to above. This isbecause of the relatively small surface area of the cavity and therelatively large height of the sidewall portion 146 of the packagearound that cavity. Attempts to apply the film 164 as part of a largerfilm result in tearing or separation of the polyimide film as a resultof exceeding its elastic limit or a failure of that film to come intoproper contact with the chip 130.

In accordance with the present invention, this problem is overcome bycutting an individual piece of the polyimide film to fit within thecavity and applying the bonding pressure thereto via a high temperatureelastic pressure block 167 (FIG. 6) which may preferably be made of hightemperature silicone rubber.

In FIG. 5, the chip 130 has been bonded to the bottom of the recess 145in the package by use of an adhesive or solder 138, depending on thepreferred bonding technique for the package in question. A glue layer162A has been deposited on the upper surface of the chip 130, includingits contact pads 132, and on the shoulder 142 and the contact lands 144of the package 140 and at the bottom of the recess 145 between the chipand the package shoulder. This adhesive is preferably a polyetherimideavailable from General Electric Company under the trade name ULTEM 1000®and is deposited by spraying a solvent solution as taught in U.S. Pat.No. 4,783,695 entitled, "Multichip Integrated Circuit PackagingConfiguration and Method" and U.S. patent application Ser. No. 312,536filed Feb. 17, 1989, as a continuation-in-part of U.S. patentapplication Ser. No. 156,318, filed Feb. 16, 1988, and entitled, "Methodof Bonding a Thermoset Film to a Thermoplastic Material to Form aBondable Laminate". The spray solution preferably comprises 10% byweight ULTEM 1000® , 50% by weight acetophenone and 40% by weightmethylene chloride. This solution is sprayed onto the integrated circuitand the package shoulder while masking the sealing ring portion 148 ofthe package. Consequently, the glue layer 162A is typically alsodisposed at the bottom of the recess 145 between the chip 130 and theshoulder 142 of the package and may also be disposed on the sidewalls ofthe cavity 145 and the chip 130. The glue in the bottom of this recessdoes not present any problems, but also is not involved in the bondingof the dielectric layer 164. A piece of a polyimide film 164 which maypreferably be KAPTON® is cut to fit within the sealing ring 148 and tocover substantially all of the shoulder 142 of the package. A layer 162Bof the same glue is applied to what will be the lower side of thispolyimide film 164 and dried. In both cases, the drying may preferablybe done at a temperature of 160° C. for a period of approximately 5minutes and then at a temperature of 290° C. for approximately 5minutes. This drying is to remove the acetophenone and methylenechloride solvent in which the desired ULTEM 1000® is dissolved for sprayapplication. After both glue layers are dried, the polyimide layer isinserted in the cavity of the package in preparation for bonding thispolyimide film to the integrated circuit chip 130 and the shoulderportion 142 of the package.

In order to bond the film 164 in place, a high temperature siliconerubber pressure pad 167 which has been cut to fit the cavity of thepackage is placed over the film 164 and a buffer polyimide film 165(FIG. 6). The buffer layer 165 of polyimide film is included between thepolyimide film layer 164 and the silicone rubber pressure pad 167because silicone rubber is known to poison polyimide films at hightemperatures (above about 200° C.). This poisoning is believed to be dueto a reaction between the polyimide film and the silicone rubber. Thebuffer polyimide film layer protects the package polyimide film 164 fromcontact with the silicone rubber and thereby prevents deterioration ofthe package polyimide film 164.

The structure is placed in a bonding furnace which is evacuated toeliminate air from within the gap between the integrated circuit and thepackage shoulder. The film 164 is bonded to the device and package byslowly heating the structure to the vicinity of 250° C. and by applyinga pressure of 30 psi to the upper surface of the silicone rubber pad 167by use of bladder membrane 172. The heating is stopped while thepressure is maintained until the structure cools to the vicinity of 100°C. Under these conditions, the adhesive layers 162A and 162B merge toform a single adhesive layer where they are disposed in contact witheach other and they permanently bond the polyimide layer 164 to the chip130 and package 140. If it is desired to remove that polyimide film 164at a later time, it may be removed by heating the structure to thevicinity of 250° C. and lifting the polyimide film off the chip andpackage. A residue of the ULTEM® polyetherimide layer is left on thechip and package after such removal, but may be removed by appropriatesolvents such as a mixture of acetophenone and methylene chloride. Oncethe package, chip and dielectric layer 164 have cooled, the siliconerubber pressure pad 167 and the buffer polyimide film 165 are removedfrom the package. Interconnections between the chip pads and the packagecontact lands are then formed in the standard method for the highdensity interconnect system as disclosed in U.S. Pat. No. 4,783,695referred to above.

In FIG. 7, the chip and package are illustrated after bonding of thepolymer film to the chip and package and removal of the silicon rubberpad 167 and the buffer polyimide layer 165. The two adhesive layers 162Aand 162B have merged into a single layer 162.

To complete the package, conductors 168 are formed on the dielectriclayer, the insulating pad 170 is disposed in the package cavity on topof the high density interconnect structure and the package is sealed bylid 149 (FIG. 3). The completed package 140 and the remainder of theelectronic system 110 are then mounted in the object 108 on structuralmember 120.

Thus far, the discussion of this structure has been in terms of a singleintegrated circuit disposed in a package and FIGS. 1-7 each illustrateonly a single integrated circuit for clarity. This technique andstructure is equally applicable to multiple integrated circuits 230packaged in a single package 240 as shown in FIG. 8 in plan view withthe cover removed. The integrated circuits 230 may preferably be placedas close together as possible, essentially edge-to-edge. This providesseveral advantages. First, the connections between chips are kept asshort as possible. Second, the gap which must be spanned by thedielectric layer 264 (not shown) is minimized, thereby maximizing theacceleration forces which the dielectric layer 264 and the conductors268 thereon can survive. The dielectric layer 264 is preferably appliedin the same manner as discussed above and the interconnectionmetallization is formed in the standard way. As can be seen, theintegrated circuits 230 are connected to contact lands 244 of package240 and to each other by conductors 268 disposed on the dielectric layer264 (not shown). The conductors 268 make contact with the underlyingconductors through via holes in the dielectric layer. Additionaldielectric and metallization layers may be applied if needed because ofthe complexity of the interconnections among the integrated circuit andthe package contact lands.

As can be seen, the high acceleration object 110 is free of wire bonds.As a result, the electronic system can operate continuously from aperiod where the object 110 is at rest, through a high acceleration ofup to 100,000 g or more, through a period of constant velocityoperation, through a period of deceleration and into a second period ofat rest operation.

It is preferred to mount the electronic system so that its greatestacceleration is in the upward (positive Z-direction) in the figures.Thus, the Z axis is a reference axis which is disposed parallel to theexpected direction of the application of the unbalanced forces which itis desired to prevent from damaging the electronic system. The highdensity interconnect system of connections is substantially insensitiveto the direction of acceleration. However, the bond holding the chip tothe package and the semiconductor chip itself may be fractured byexcessive accelerations in the XY plane or in the negative Z-direction.Further, the package itself may come loose from its mountings under suchaccelerations. The glue 162A at the bottom of the gap 143 can aid inretaining the chip in place. Filling the gaps with glue further securesthe chips. Thus, the overall structure of the object itself and theorientation and mounting of the electronic system as a whole and itsindividual components themselves must be carefully designed to withstandthe expected magnitude and direction(s) of accelerations which theelectronic system must survive. With an electronic system in accordancewith these teachings, that design becomes possible whereas with the wirebond connected integrated circuits of the prior art, that design is notpossible.

The package and sidewall 146 and the lid 149 may be omitted if ahermetic seal is not required. In that case, the circuit is packagedessentially in the manner taught in U.S. Pat. No. 4,783,695.

The overall electronic system includes appropriate voltage sources suchas solar cells, batteries, fuel cells or capacitors which store orprovide sufficient charge to operate the electronic system duringacceleration and subsequent thereto. For some systems, the desiredperiod of operation is short enough that a battery or other power supplymay be used as a source of pre-acceleration power and ceramic or otheracceleration-surviving capacitors may be used to provide the power tocontinue system operation during and after acceleration where thebattery or initial primary power source fails during acceleration.

While the invention has been described in detail herein in accord withcertain preferred embodiments thereof, many modifications and changestherein may be effected by those skilled in the art. Accordingly, it isintended by the appended claims to cover all such modifications andchanges as fall within the true spirit and scope of the invention.

What is claimed is:
 1. A high density interconnect structurecomprising:a package base having a cavity therein including a recess inthe bottom of the cavity in which a semiconductor chip having contactpads thereon is disposed, said package base including contact landsdisposed on a shoulder within said cavity adjacent said recess, saidcontact pads and said contact lands being disposed in substantially acommon plane; a polymer dielectric layer about 1-2 mils thick disposedon the exposed major surface of said semiconductor chip and on saidcontact lands and extending across any gap between said chip and saidshoulder; a plurality of via holes in said dielectric layer disposed inalignment with selected ones of said contact pads of said semiconductorchip and said contact lands of said package; a plurality of conductorsdisposed on said polymer dielectric layer interconnecting selected onesof said chip contact pads and said package contact lands and extendinginto appropriate ones of said via holes to provide those connections;said polymer dielectric layer and said interconnecting conductor patternbeing recessed within the cavity of said package.
 2. The structurerecited in claim 1 further comprising a package lid bonded to saidpackage base to hermetically enclose said semiconductor chip, saiddielectric layer and said interconnecting conductors within saidpackage.
 3. The structure recited in claim 2 further comprising:a soliddielectric block between said semiconductor chip and said lid extendingfrom said polymer dielectric layer and said conductors to said lid to atleast partially support said lid.
 4. The structure recited in claim 1wherein:there is a gap between said chip and said shoulder; and saiddielectric layer is unsupported where it spans said gap.
 5. Thestructure recited in claim 4 wherein:the portions of said plurality ofconductors which span said gap are about 0.1-0.5 miles thick wherebysaid dielectric layer is capable of supporting the portions of saidconductors which span said gap while experiencing said unbalanced forcesin excess of those induced by an acceleration of 20,000 g to preventshort circuit faults, open circuit faults and other unacceptableconductor degradation.
 6. The structure recited in claim 1 wherein:saidpolymer dielectric layer has a substantially uniform thickness.
 7. Thehigh density interconnect structure recited in claim 1 wherein:saidcontact lands are integral with external conductors of said package. 8.The structure recited in claim 1 wherein:there is a gap between saidchip and said shoulder; and which further comprises a dielectricmaterial filling the gap.